Sampled data hybrid analogue-digital computer system

ABSTRACT

A hybrid analog-digital computer apparatus, particularly applicable in controlling complex servomechanisms such as aircraft flight control actuation and display systems, comprising a time shared or multiplexed operational amplifier adapted to receive analog signals from control system inputs and command sources through a large plurality of solid state switching devices at controllable gain levels and to supply outputs through a plurality of similar output switching devices to a plurality of analog storage devices, such as simple capacitors, the charges on the capacitors being fed back to the amplifier input in predetermined controlled manners for performing various control functions; the computer outputs being the resultant charges on one or more of said capacitors and being supplied to the actuation and/or display devices. Through predetermined control of the input and output switches, one or more input signals are selected and various computational operations thereon are performed as required for proper system control. The signals to be selected and the computations to be performed are under the control of a programmed digital memory, the sequential word and word bit outputs of which determine the sequence and orders respectively of switch operations and the signal gains required. The digital format of the program output and the high-speed operation of the solid-state switches provide extremely rapid sequencing of desired computations while the data always remains in analog form thereby retaining the precise resolution of analog computers while providing the high-speed capability of digital computers. Since all the computations are determined by the programmed memory, the computer is adaptable to control systems of widely different characteristics and complexity merely by the addition or deletion of switches and storage capacitors and by inserting the proper program into the memory. Hence, in terms of aircraft automatic flight control, a truly &#39;&#39;&#39;&#39;universal&#39;&#39;&#39;&#39; flight control system.

United States Patent [72] inventor Richard E.Andeen Phoenix, Ariz. [21]Appl. No. 646,549 [22] Filed June 16, 1967 [45] Patented Apr. 6, 1971[73] Assignee Sperry Rand Corporation [54] SAMPLED DATA HYBRIDANALOGUE-DIGITAL COMPUTER SYSTEM 16 Claims, 9 Drawing Figs.

[52] U.S.Cl 235/150.5, 235/150.5l,235/l50.52,235/150.2,235/15l.1 [51]Int.Cl G06j1/11 [50] Field of Search... 235/150.3, 150.31, 150.4, 150.5,150.51, 150.52, 150.53, 193, 183; 340/1725 Primary Examiner-Eugene G.Botz Assistant Examiner-Joseph F. Ruggiero AItomeySamuel C. YeatonABSTRACT: A hybrid analog-digital computer apparatus, particularlyapplicable in controlling complex servomechanisms such as aircraftflight control actuation and display systems, comprising a time sharedor multiplexed operational amplifier adapted to receive analog signalsfrom control system inputs and command sources through a large pluralityof solid state switching devices at controllable gain levels and tosupply outputs through a plurality of similar output switching devicesto a plurality of analog storage devices, such as simple capacitors, thecharges on the capacitors being fed back to the amplifier input inpredetermined controlled manners for performing various controlfunctions; the computer outputs being the resultant charges on one ormore of said capacitors and being supplied to the actuation and/ordisplay devices. Through predetermined control of the input and outputswitches, one or more input signals are selected and variouscomputational operations thereon are performed as required for propersystem control. The signals to be selected and the computations to beperformed are under the control of a programmed digital memory, thesequential word and word bit outputs of which determine the sequence andorders respectively of switch operations and the signal gains required.The digital format of the program output and the high-speed operation ofthe solid-state switches provide extremely rapid sequencing of desiredcomputations while the data always remains in analog form therebyretaining the precise resolution of analog computers while providing thehigh-speed capability of digital computers. Since all the computationsare determined by the programmed memory, the computer is adaptable tocontrol systems of widely different characteristics and complexitymerely by the addition or deletion of switches and storage capacitorsand by inserting the proper program into the memory. Hence, in terms ofaircraft auto- I matic flight control, a truly universal flight controlsystem.

OUTPUT -I- f 12 1 l BUFFER R INEP1UT GA lN H [MFR 33 I C2 14 4 CONTROLAMPL- S (LADDER) S S 13 a BUFFER S5 f DIGITAL PROGRAM ANDINSTRUCTIONREGISTER INSTR. s s $4 SAMPLED DATA HYBRID ANALOGUE-DIGITAL COMPUTERSYSTEM SUMMARY OF THE INVENTION puters for use in controlling complexservomechanisms, such as for example, aircraft automatic pilots. In suchsystems, data in the form of analog electrical signals supplied from aplurality of signal sources, such as displacement and rate gyroscopicsensors, accelerometers and various path control signal sources areselected, operated upon in accordance with particular mathematicalfunctions and combined in particular manners, to provide output signalsto servoactuators for operating the aircraft control surfaces (and/or todisplay devices of instrument systems). The present invention concerns acomputer of the sampled data type for performing the selecting,computing and combining functions above-noted and comprises a singletime shared or multiplexed operational amplifier adapted to add andsubtract analog signal quantities through a plurality of input switchesand to store the results through a plurality of output switches onmemory devices, such as capacitors, which results are called out at theproper times as analog outputs and/or feedback signals. By propersequencing of switch operations, any linear filtering function can beperformed. Certain nonlinear functions such as limiting may be similarlyperformed. The sequence of switch operations is determined by thecontents of a digital program memory. Such a system has a number ofadvantages over a completely analog or a completely digitalmechanization. For example, changes in computation are made by memoryprograrnming rather than by hardware modifications; no complexanalog-to-digital or digital-to-analog conversions are required, i.e.,all data is processed, stored and called out in analog form therebyretaining the high degree of resolution of an analog system yetproviding the high-speed capability of a digital system. Furthermore,since the computer of the present invention has fewer active parts thana pure digital computer of equivalent capability, it has bothreliability and cost advantages.

The basic elements of the sampled data computer of the present inventioncomprise an operational amplifier which may be a high gain differentialamplifier with both inverting and noninverting inputs (or alternativelyseparate inverting and noninverting amplifiers) and a feedback resistorconnected from the amplifier output to the inverting input. The inputsto the amplifier are controlled in accordance with the conducting ornonconducting states of a plurality of input switches while the outputthereof is applied to a plurality of analog signal storage devices, suchas simple capacitors, in accordance with the conducting or nonconductingstates of a plurality of output switches, the latter switches alsocontrolling the output of the computer. The input switches constitutethe read logic while the output switches constitute,the store logic. Thefunctions to be performed by the computer is determined by the propersequence and combinations of switch operations which in turn ispredetermined by the digital program memory.

The program memory may be perfectly conventional and preferably is ofthe nondestructive readout type (i.e., programmed for a particular typeof vehicle) including, in addition to the usual interrogate and senseamplifiers, the logic required to cause the instructions to be read outin the sequence and also the logic to change the sequence as required bya particular flight control mode.

The principles of the present invention will be applied in performingvarious computations commonly required for automatic flight controlpurposes or for controlling similar complex servomechanisms; forexample, summation, integration, complex filtering, limiting,multiplication, etc. The filter may be of the first, second or higherorder types. A typical automatic flight control system embodying theprinciples of the present invention is disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS The principles involved in carryingout the present inventive concepts will be more apparent when consideredin connection with illustrations of specific embodiments thereof setforth in the accompanying drawings wherein:

FIG. 1 is a block diagram of a basic summation circuit employing anoperational differential amplifier;

FIG. 2 is a block diagram of the sampled data computer of the presentinvention programmed to perform an integration function;

FIG. 2A is a graph of the output of the sampled data integrator of FIG.2 in response to a step input;

FIG. 3 is a block diagram of the present sampled data integratorarranged to simultaneously integrate two independent signals; additionalconnections being shown for performing on said signals two independentfirst order of low-pass filter functions;

FIG. 4 is a block diagram of a general second order sampled data filter;

FIG. 5 is a block diagram of the purely analog equivalent of the generalsecond order filter of FIG. 4 for comparison purposes;

FIG. 6 is a block diagram of a typical sampled data limiter;

FIG. 7 is a block diagram of a sampled data multiplier; and

FIG. 8 is a generalized block diagram of a typical automatic flightcontrol system embodying the sampled data computer principles of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the drawings many of thecomponents are identified by numbered letters or combinations thereof,for example C R R S etc. However, throughout the followingspecification, these numerals and/or letters will be preceded by thenumeral corresponding to the figure being discussed. Thus, for example,in the specification, the reference character 2S. identifies switch S ofFIG. 2 of the drawings, reference characters 4C and 4R,, in thespecification represent capacitor C and resistor R of FIG. 4 of thedrawings, and so on. Numeric reference characters will also be used in aconventional manner.

Referring now to FIG. I, the basic component of the sampled datacomputer of the present invention is a high gain differential amplifierindicated throughout the specification by reference character 10. It maybe a conventional direct coupled difi'erential amplifier havingnoninverting and inverting inputs l1 and 12 respectively and an output13 although it will be understood that separate noninverting andinverting amplifiers may be employed. A feedback resistance IR, isconnected from the output to the inverting input 12. Since signalsummation is the basic required function of the present system, it hasbeen shown separately in FIG. 1 and although conventional, it has beenillustrated in the interest of completeness of the disclosure. Resistors1R to 1R, are interposed between the analog signal inputs 1E to IE andthe inputs l1 and 12 of amplifier 10. Thus with feedback resistor 1R,connected, the output signal IE, on lead 13 is:

Rf RI 4 -e E0=(*;)E1+("R2)E2 R3 E3 R4 E4 The proper gains for the inputsignals are provided by the selection of values for the resistors 1R, toIR,,. Clearly, if any of the inputs are zero, their corresponding termin (1) will be zero. Thus, FIG. 1 discloses a means for summing,inverting and multiplying by proper gains a plurality of analog inputsignals.

The basic principles of the sampled data computer of the presentinvention are illustrated in FIG. 2 wherein the summation capabilitiesof the differential amplifier 10 of FIG. 1 is employed together withadditional components to provide a sampled data integrator function. Theadditional components comprise a number of switches 28, to 28 and twoanalog storage devices, such as simple capacitors 2C. and 2C Alsoprovided is a conventional ladder network (represented here by 2R forcontrolling the gain of the analog input 2E a second amplifier feedbackresistor 2R, f, buffer amplifiers I4 and I5 and a digital programmer andinstruction register 20 for operating the switches. The switches 2S to28 may be transistor switches and are herein shown as field effecttransistors. As stated above, the digital program memory determines thecomputation to be performed in FIG. 2, i,e., the integration function.The output of the program and instruction register 20 operates theswitches 28 to 28 in a predetermined order at a fixed sampling rate andin a predetermined sequence. The sampling rate is high enough so thatthe output appears continuous for practical purposes, i.e., may be onthe order of thousands of samples per second, but may be altered ifrequired depending upon the desired gain and time constants ofintegration by program modification.

The word and bit program for integration is an illustrated within block20. During one sampling interval, Instruction 1, the switch positionsare 10011 (1 indicating a closed or conducting switch) and during thenext interval, Instruction 2, they are 01100. The integral function isobtained as follows: Assuming no initial charge on either capacitor atthe initiation of program Instruction 1, and a step input of 1 volt isapplied at 2B, through 2R,, to the noninverting input of amplifier 10,the voltage applied to 2R, from 2C through 28 will be volt, and theoutput of amplifier 10-will be 1 bolt (assuming R =R,). Memory capacitor2C will, therefore be charged to a value of 1 volt through closed switch28 the output of 2B,, of the computer being zero since the charge on 2Cis zero. During the next sampling interval, Instruction 2, the l-voltcharge on 2C will be applied to 2R, through switch 2S to thenoninverting input 11 of the amplifier 10 and, since 28 is now open,this 1 bolt will be applied to the memory capacitor 2C through 28 whichwill charge 2C to this voltage value, the computer output 2E being thesame, 1 volt. During the next sampling interval, Instruction 1 again,the 1 volt on 2C is applied to 2R, through 25. to be added to the input213,, being again closed, whereby the output of amplifier is now 2 voltswhich charges 2C to this value through 25 The output 2E will remain at 1volt. During the next sampling interval, Instruction 2 again, the 2volts on 2C are applied to 2R, through 25 and 28 being again open, theamplifier output will be 2 volts and 2C will be charged to this value sothat the resultant charge on 2C will be 2 volts, which is the outputvalue of 2B,. During the next sampling interval, Instruction 1, the 2volts on C are added to the input, the amplifier output being 3 voltswhich is applied to 2C charging it to this value. During the nextinterval, Instruction 2, the 3 volts on C are applied to C throughamplifier 10 to charge it to this 3-volt value which is the value of theoutput 2B,. This sequence continues as long as the program calls for anintegration of the input 213 with the output 2E increasing 1 volt everyother instruction cycle. In practice, it is preferable to include wordbits for providing a space between switch closings and openings toprevent any cross talk from occurring.

The integrator of FIG. 2 may be simplified by eliminating 28 andconnecting the output 2E, at the junction between 28 and 28 This resultsin an increase of 1 volt at the output 213,, after each instructionrather than an increase of 1 volt after every other instruction cycle,as in FIG. 2. However, the somewhat more complicated operation of thearrangement of FIG. 2, wherein capacitor 2C provides a temporary memory,will be justified when considering the multiplexing capabilities of thepresent invention as described below.

The output of the sampled data integrator of FIG. 2 is illustrated inFIG. 2A and is a typical staircase function characterized by a samplingperiod T and a delay 0' between the imposition of an input at 213 and anincrease in the output 2B,. The sampling period T is fixed at a valuewhich depends at least upon the desired gain and time constants of theintegrator while the delay depends upon the charge time of thecapacitors 2C and 2C and also upon the switching logic. Since 0' cannotexceed T, the integration process may be expressed by the differenceequation (referring to equation (1)):

where E (n) is the value of E during the nth sampling period. Equation(2) may be expressed in terms of the (z) transform variable as follows:

l-L J E (z) 1 a In practice R; and R, are never exactly equal whichresults in an imperfect integrator having a time constant givenapproximately by;

h W ere ,=R 1-A/100) and For typical values of Tequal to 0.01 second andA equal to 0.1 we have an integrator time constant 7 equal to 5 secondswhich is acceptable for most practical appreciations. For longer timeconstants either the sampling period of the computer system must beincreased, or the tolerances on the impedences R; and R, be controlledmore closely, or a combination of both.

It will be noted that the integrator of FIG. 2 differs substantiallyfrom a conventional analog integrator which must have a very largecapacitor connected in feedback around a high-gain amplifier, the figureof merit of such an integrator being a function of the holding capacityof the feedback capacitor. Furthermore, in a complex system, such as anaircraft autopilot, for example, a large number of individualintegrators are required, adding to system complexity and cost. Also,the sampled data integrator of the present invention differs from aconventional digital integrator in that no analog-to-digital anddigital-to-analog conversion is required. Also, a purely digitalintegrator processes each signal individually by sequential arithmeticoperations. It is thus more complex and signal resolution lost due tothe required conversions.

The sampled data integrator of the present invention requires but quitesmall capacitors, for example, 0.01 p.f., since the size affects onlythe charge and discharge time constants and not the integrator gain ortime constants. Furthermore, as will become evident below, only oneamplifier is required for the complete computing system since itsoperation may be readily multiplexed. But more important, it does notrequire data conversion or quantization and hence retains the resolutionof a purely analog system.

The above-described sampled data computation technique lends itselfreadily to multiplexed operation for performing a plurality ofcomputations at the same time and also for performing more complexcomputations. This is accomplished by expanding the circuit of FIG. 2 toinclude a number of memory capacitors and consequent larger number ofcharging switches and sampling switches. While the programmer for thearrangement of FIG. 2 may constitute a relatively simple microcircuitlogic, the more complex computer system may require that the sequentialprogram be retained in a digital memory which may be of any conventionaltype, such as a 5 core matrix'or drum.

Referring now to FIG. 3, a more complex sampled data computer isillustrated. In this arrangement two integrators are multiplexed toprovide separate integration of two independent input quantities. Herethe differential amplifier receives inputs 3E and 313 at itsnoninverting input 11 through input switches 3s and 38 and gaincontrolling resistances 3R and 3R respectively. The amplifier output 13is coupled to memory capacitors 3C 3C and 3C through charging switches38 35 and 38 respectively. The outputs 3E and 3E are taken from 3C and3C and are also applied to 3R, together with the output of the timeshared capacitor 3C through 3S 38 and 38 respectively. The digitalprogram and instruction register controls the sequence of switchoperation for this computer arrangement and the program is set forthwithin the block. The separate integration of two independent inputsignals is accomplished by four instruction .words of eight bits eachcontained within the program memory. The operation of the dualintegrator of FIG. 3 is similar to that of the single integrator of FIG.2. The gain constant of each integrator is dependent upon the switchingor sampling frequency and the value of 3R and R which values, as in thecase of FIG. 2, may be predetermined by an additional program outputcontrolling a transistor switched ladder network.

FIG. 3, may be easily modified to provide a further computationalcapability of the sampled data system of the present invention; i.e., tosynthesize separate first order or low-pass filters. This may beaccomplished by simply connecting the outputs 3E and 35 of theintegrators back to the inverting input 12 of differential amplifier 10through two additional input switches and corresponding input resistorsas shown by the dashed lines in this FIG. These feedback connectionsprovide the capability of synthesizing separate first order or low passfiltering of each of the inputs 3E, and 3E the time con stants beingdetermined by the values selected for the resistors connected to theinverting input. The digital programmer 20 will, therefore, include twoadditional word bits for the additional switches, both being actuatedpreferably simultaneously with 35 and 38 respectively.

The expansion of the sampled data computer of FIGS. 2 and 3 to performeven more complex computations is illustrated in FIG. 4. This FIG. showsa sampled data computer for synthesizing the general second order filterfunction:

The overall configuration is similar to those of FIGS. 2 and 3 andcomprises the multiplexed differential amplifier 10, a bank of memorycapacitors 21 with their charging switch logic 22, a bank of summingresistors 23, one or more of which may comprise programmed laddernetworks, and an input switch logic 24, the switch logics (and laddernetworks, if desired) being controlled from the digital program andinstruction register 20. The program 20 controls the operation of theswitch logic in accordance with five instruction words of 13 bits eachas set forth within the program block 20. In general, memory capacitor4C holds the filter output, capacitors 4C and 4C are the integratoroutputs while capacitor 4C constitutes a temporary storage shared by thetwo integrators as in the arrangement of FIG. 3. While the use of thetime shared capacitor results in considerable savings in systemcomplexity, it will be understood that two capacitors for eachintegrator may be used as indicated in connection with the discussionsof FIG. 2.

As an aid to understanding the operation of the sampled data secondorder filter of FIG. 4, the continuous analog equivalent of a typicalsecond order filter is illustrated in FIG. 5. It will be noted that thefeed forward impedances Sa 5a,, 5a and the feedback impedances 5b,, Sbof the second order filter of FIG. 5 find their correspondingcounterparts in 4R 4R, 4R,, and 4R in the summing resistor bank 23 ofFIG. 4. Also, the process summing amplifier No. 1 and processintegrators No. 2 and No. 3 of FIG. 5 correspond to the similarlynumbered instruction steps of the digital program 20 of FIG. 4.

Higher order filter functions may be formed in the same manner as thesecond order filter function of FIG. 4 by correspondingly increasing thenumber of process integrators and their corresponding feedforward andfeedback circuits. Thus, the number of storage capacitors, chargingswitches and input switches is dependent upon the order of the filter itis desired to synthesize.

In controlling most complex servomechanisms, it is often required toperform a number of nonlinear computations. The sampled data computer ofthe present invention is also arranged to synthesize this type offunction, e.g., limiting and multiplication. The arrangement shown inFIG. 6 provides normal limiting.

It is desired that the sampled data computer be programmed to providelimiting of a selected input voltage to any desired value, i.e., avariable limit, and yet accomplish this with a minimum of additionalcomponents. The arrangement shown in FIG. 6 is programmed to accomplishthis by using a single fixed voltage limiter and to program the gain ofthe input signal depending upon the desired limiting value.Specifically, the input signal 6E to be limited is applied to laddernetwork 30 where the desired impedance Rf R corresponding to the desiredlimit value, is selected by digital programmer 20 through ladderswitches 65 to 65 this signal being applied to the noninverting input 11of differential amplifier 10. It should be noted that a typical laddernetwork is shown in FIG. 6 and may be of the thin film type havingshorts controlled by transistor switches controlled in turn from thedigital program 20. This is typical of the ladder networks referred toin connection with the other FIGS. The output of amplifier 10 is fedback to the inverting input 12 through switch 65 and zener diodes 32 inparallel with R,. With this limiter, two program instructions arerequired. The first calls for the closing of switches 65 68 and 68 andthe opening of switches 68 and 65 which provides a fixed limit on theamplifier output and for the charging of 6C,, also for the selection ofthe desired impedance from ladder 30 through switches 68 to 65corresponding to the desired limit value, i.e., (R=R, /K,). The secondinstruction calls for the opening of switches 68 68 and 65 and theclosing of switches 68 and 68 which applies the voltage on C back to theladder 30 and removes the fixed limit on the amplifier output, and alsofor the selection of the desired impedance from ladder 30 throughswitches 68 to 68 corresponding to the desired limit value, i.e.,(R=K,R,). (K is the ratio of fixed limit 1 to the desired limit I i.e.,K,=lc/ 1p.) In effect, during the first instruction time the signal atamplifier output 13 is E =lim [K E and during the second instructiontime the desired output 6EX ISEx =l/K, E,,. If it is desired to limitthe input to a different value I,,, then the value of K, in theexpression is adjusted appropriately, this determining the switchingprogram for switches 65 to 65 In the limiter arrangement of FIG. 6, anysuitable voltage limiter device may be used, the Zener diodesillustrated being preferable since they require no operating power aswould back-biased diodes.

The limiter arrangement of FIG. 6 may be modified as shown by dashedlines to provide a deadband function. For this case, the output of thelimiter 6E is subtracted, as at summing point 33, from the originalinput signal 6E to provide the desired deadband function E =E -E Theinstructions contained in the program are the same.

In many servomechanisms, a multiplier is required for gain changing orfor function generation. The quarter square technique is well suited tohigh speed and moderate accuracy requirements. How this is provided bythe sampled data com puter of the present invention is illustrated bythe arrangement shown in FIG. 7. Specifically, the input signals to bemultiplied 7B,, and 7E are applied to switches 75 78 and 78 which areselectively closed or opened in accordance with the digital program 20.Five program steps are required to obtain the product (E )X(E,,). In thefirst instruction switches 75 78 and 78 are closed and the sum E -l-E isformed and stored as a voltage on 7C,. In step 2 the voltage on 7C isapplied to a squaring circuit 19, which may consist of a conventionaldiode on transistor function generator circuit or other suitable squarelaw device and the result is applied through switch 78 to 7C Ininstruction 3 the difference E ,E,, is formed by closing switches 7S and78 and the result is stored as a voltage on 704% 0 -c,1= 12.) (By) 7)The sampled data computer of the present invention is expanded into acomplete programmed computer for automatic flight control applications,a block diagram of which is illustrated in FIG. 8. It includes theintegration, complex filtering, limiting and multiplication functionsset forth in the previous FIGS. as well as logical functions required bymode switching together with a means for programming the gains of thevarious system control signals.

A conventional automatic flight control system includes (for each axisof control) stabilization sensors 40 which usually comprise displacementand rate sensors, such as displacement and rate gyroscopes and/oraccelerometers; navigation sensors 41 which usually comprise compasssystems, radio receivers such as VOR-ILS, Tacan, Doppler etc. receiversfor flight path definition or complete inertial navigators; commandsensors 42 such as, for example, control stick or control wheel steeringsensors for manual maneuvering; and a mode selector 43 for selecting thedesired mode of operation of the flight control system. The aircraftcontrol surface 44 is moved in accordance with the output of the systemthrough hydraulic or electric servoactuator 45 and servoamplifier 46,buffer circuits 47 being provided for coupling the output signals of thesampled data computer memory elements to the servoamplifier 46. All ofthe foregoing elements may be conventional and are well known in theflight control art.

In conventional flight control systems, the various sensor signals areseparately processed and summed to provide an output command to theservoactuators. This involves separate and complex circuitry and oftenconsiderable circuit redundancy. In accordance with the teachings of thepresent invention, the signal processing and summation is accomplishedby means of the programmed sampled data technique described in theforegoing. Thus, the basic components of the sampled data computer ofFIG. 8 are, as in the abovedescribed embodiments, the multiplexedoperational amplifier 10, analog memory elements 50, input switches 51constituting the read logic, limiting (and deadband) circuits 53, andvariable gain ladders 54 for programming the system gains and which alsoinclude squaring circuits for multiplication. A logical section 55 isprovided for determining which control modes are to be effected at agiven time. All of the foregoing elements are controlled from thedigital program memory 56 and instruction register 57.

The memory 56 and instruction register 57 may be of any conventionaltype. The memory 56 preferably has a nondestructive readout and isnonvolatile. The number of instruction words and word bits are dependentupon the number of signals to be processed and the process functions tobe performed. The instruction register may be the conventional chain offlip-flops set by the memory word bits which in turn operate the readand store logic switches 51 and 52 respectively, the variable gains 54and limiter circuits 53. While the logicaloperations required of theflight control system may be performed by the sampled data computeritself, for example,

as by using coded inputs or a programmable logic section at theamplifier input and a comparator responsive to the output of theamplifier 10 for controlling the register 57, a separate logical section55 is preferred since its operation is capable of higher rates than thesignal processing operation and hence the logical operations need nottake up time needed for the signal processing functions.

Automatic flight control systems vary in complexity in accordance withthe aircraft control functions to be be automated and the type ofairframe to be controlled. For example, they vary from a simple singleor multiple axis stability augmentation system to complex systems forcontrolling the aircraft flight path in accordance with internallygenerated navigation information (inertial navigation systems), externalnavigation information such as defined by radio beams (VOR, ILS, etc.),military fire control information, etc. In accordance with the teachingsof the present invention, the flight control system requirements arepredetermined which in turn determines the number of input and outputswitches and analog memory elements necessary to perform thecomputations and signal processing necessary to fulfill theserequirements. The order in which these functions are performed is alsopredetermined and is controlled by the program memory. In practice, therequirements of a generalized flight control system are determined and acomputer including the required memory and switching elements isconstructed while the requirements of the application thereof to aspecific installation (e.g., aircraft type and mission) may be met by aspecific program corresponding to these specific requirements.

For example, consider a three axis stability augmentation system. Thebasic system comprises roll, pitch, and yaw rate gyros, signalprocessing computer and servoamplifiers and actuators. The sampled datacomputer performs the signal processing required, which processingincludes second order filtering of the gyro signals, limiting thesesignals to a desired level and selecting the proper signal gains. Thus,sampled data computer systems will include the second order filterarrangement of FIG. 4 and the limiter of FIG. 6. The input logic 51 musthave the capacity to select from a minimum of 16 signals, three for eachgyro 40, four for the second order filter feed backs, and three for thelimiting function. Two five bit ladder gain changers 54 are provided,one for selecting the desired gain level of the sampled gyro signals andthe other for selecting the desired limit for the sampled gyro signals.The output of operational amplifier 10 will be applied to 12 memorycapacitors 50, four for each of the three control axes, through acorresponding 12 output logic switches 52. The foregoing establishes amemory word length of about 40 bits. The number of memory words is alsodetermined from the foregoing; 15 for the filter function, six for thelimiting function and others for the required summing operations, atotal of about 25 words.

For implementing a complete flight control system, additional switchingis provided for selecting signals from navigation sensors 41, commandsensors 42, and mode selector 43, the latter establishing the inputs forlogical section 55. Additional gain change ladders are provided forparameter control purposes as well as for establishing the limits to beimposed on the signals. Also, in connection with automatic path control,for example, integration is a requirement so that the circuits of FIGS.2 and/or 3 may be included in such complete autopilot. The programmemory capacity will accordingly be increased to implement the morecomplex system, for example, it may be increased to or more words of asmany bits, a capacity presently available in biax or other solid statememory devices.

In a practical application of the present invention in a completeautomatic pilot, a sampling rate of 100 times per second is reasonableand the number of computations or instructions to be performed persecond is about 100. Thus, the

computer clock frequency must be 10 kc., a frequency well.

within the capability of present day digital computers.

While the invention has been described in its preferred embodiments, itis to be understood that the words which have been used are words ofdescription rather than of limitation and that changes within thepurview of the appended claims may be made without departing from thetrue scope and spirit of the invention in its broader aspects.

lclaim:

l. A sampled data computer for performing predetermined computation onanalog information signals comprising:

a. a high gain difi'erential amplifier means having noninverting andinverting inputs and an output and an impedance means coupling saidoutput to said inverting input for adding and subtracting signalsapplied to said amplifier inputs;

b. means supplying analog information signals to at least one of saidamplifier inputs;

c. a plurality of analog signal storage means responsive to the outputof said amplifier;

d. a plurality of switch means having conducting and nonconductingstates for connecting said amplifier output to said signal storage meansand for connecting said storage means back to said amplifier inputs forcombining the signals stored therein with said information signals;

e. digital memory means connected to control said plurality of switchmeans in accordance with a predetermined program, said programcomprising a plurality of sequential word instructions, each wordcomprising a plurality of bits corresponding to said plurality ofswitches for controlling the states of said switches, said programdetermining the computation to be performed on said analogue informationsignal; and

. an output means coupled with at least one of said signal storage meansand responsive to the resultant signal stored thereon.

2. The sampled data computer as set forth in claim 1 wherein said analogstorage means comprises capacitor devices.

3. The sampled data computer as set forth in claim 1 wherein saidswitching devices comprise electronic switches of the transistor type.

4. The sampled data computer as set forth in claim 1 for computing theintegral of said information signal wherein:

a. said information signal is applied to said noninverting input of saidamplifier;

b. said signal storage means comprises at least first and second signalstorage devices;

c. said plurality of switches comprises at least first and secondswitches for selectively connecting said amplifier output to said firstand second storage devices respectively and third and fourth switchesfor selectively connecting the signal stored on said first and secondstorage devices respectively back to the noninverting input of saidamplifier;

d. said digital memory supplied at least two sequential instructionwords repeated over a time period each comprising at least four bits,the first instruction word bits being such that said first and fourthswitches are closed and said second and third switches are open wherebyto apply the signal stored on said second storage device to saidamplifier input and to apply said amplifier output to said first signalstorage device, and the second instruction word bits being such thatsecond and third switches are closed and said first and fourth switchesare open whereby to apply the signal stored on said first storage deviceto said amplifier input and to apply said amplifier output to saidsecond signal storage device, and so on; and wherein e. said outputmeans is coupled with said second signal storage device.

5. The sampled data computer as set forth in claim 4 further including:additional switch means and additional digital word and word bits forconnecting the output signal stored on said second signal storage meansto the inverting input of said amplifier for opposing said informationsignal whereby to provide a low pass filtering function of said analoginformation signal.

6. The sampled data computer as set forth in claim 1 for limiting thevalue of said information signal to any desired value wherein:

a. said differential amplifier output to said inverting input couplingmeans includes means for limiting the magnitude of said amplifier outputto a predetermined fixed value and limiter switch means havingconducting and nonconducting states for rending said limiting meanseffective and noneffective; and further including;

b. variable impedance means coupling said information signal to thenoninverting input of said amplifier and including switch means fordetermining the impedance to said signal whereby to determine the gainthereof; and

c. said signal storage means includes at least first and second storagemeans; and wherein d. said programmed digital memory includes a firstinstruction word for controlling said switch means such as to select thegain of said information signal, limit the same to said predeterminedvalue and supply said limited signal to said first signal storage means,and a second instruction word for controlling said switch means such asto render said limiting means noneffective, supply said stored signal tosaid variable impedance means whereby to vary the value thereof inaccordance with said reciprocal impedance value, and for storing theresulted signal in said second storage means,

7. The sampled data limiter as set forth in claim 6 further includingmeans responsive to said information signal and the output of saidsecond signal storage means for supplying an output in accordance withthe difference therebetween whereby to provide a deadband function.

8. The sampled data computer as set forth in claim 1 for computing theproduct of two analog input signals wherein:

a. said means supplying analog information signals includes switchingmeans for supplying two information signals to said noninvertingamplifier input and one of said informa' tion signals to said invertingamplifier input; wherein b. said signal storage means includes at leastfour signal storage means; further including c. a squaring circuitincluding switching means for coupling the output of one of said storagemeans to the noninverting input of said amplifier; and further includingd. impedance means including switching means for coupling apredetermined portion of the signals stored on second and third of saidstorage means to said noninverting input; and wherein c. said programmeddigital memory includes a group of instruction words for controllingsaid switch means such as to store signals proportional to the squaresof the sum and difference of said input signals on said second and thirdstorage means, respectively, and a further instruction word forcontrolling said switching means such as to supply the signals stored onsaid second and third storage means to said impedance means and theoutput of said amplifier to the fourth of said storage means, wherebythe signal stored thereon is proportioned to the product of said inputsignals I 9. The sampled data multiplier as set forth in claim 8 whereinsaid group of instruction words comprises a first instruction word forcontrolling said switching means such as to store on said one storagemeans the sum of said input signals, a second instruction word forcontrolling said switching such as to couple the signal stored in saidone storage means to said squaring circuit and to store the output ofsaid amplifier on second of said storage means, a third instruction wordfor controlling said switching means such as to store on said onestorage means the difference of said input signals, and a fourthinstruction word for controlling said switch such as to couple thesignal stored on said one storage means to said squaring circuit and tostore the output of said amplifier on said third storage means.

10. A sampled data computer system for performing a plurality ofcomputations on a plurality of analog input signals and for supplyinganalog output signals proportional to predetermined functions of saidinput signals, said system compnsrng:

a. a multiplexed high gain differential amplifier means having invertingand noninverting inputs and an output and including a feedback impedanceconnecting said output to said inverting input whereby to add andsubtract signal quantities applied thereto;

b. a plurality of analog signal storage means;

0. a plurality of output switching devices having conducting andnonconducting states for selectively connecting said amplifier output tocorresponding ones of said signal storage means depending upon thestates thereof whereby to store said amplifier output in said selectedstorage means;

(1. a plurality of input switching devices having conducting andnonconducting states for selectively connecting a plurality of signalsto said amplifier inputs depending upon the states thereof, saidplurality of signals including said analog input signals and selectedones of the signals stored on said storage means;

e. a programmed digital memory means for determining the functions to beperformed on said input signals, said digital memory providingsequentially read words, each word comprising a plurality of bitscorresponding to said plurality of switch devices, whereby to controlthe sequence and order respectively of switch states required forperforming said functions; and

f. means coupled with selected ones of said signal storage means forsupplying analog output signals corresponding to the resultant signalsstored thereon.

11. The sampled data computer as set forth in claim further including aplurality of impedances coupled between said input switches and saidamplifier inputs for determining the gains of said selected signals.

12. The sampled data computer as set forth in claim 11 wherein at leastone of said impedances comprises a resistance ladder network and aplurality of switches for selecting the resultant impedance thereof, andwherein said digital program memory includes word bits for controllingsaid ladder switches whereby to program the gains of said selected inputsignals in accordance with the function to be performed.

13. A digitally controlled, analog servomechanism comprisa. a pluralityof sensors for producing a plurality of analog signals each proportionalto one of a plurality of conditions to be controlled;

b. servomotor means for controlling said conditions;

c. sampled data computer means responsive to said sensor signals forperforming a plurality of predetermined computations thereon and forsupplying resultant output signals to said servomotor means whereby tocontrol said conditions in accordance with said predeterminedcomputations, said computer means comprising:

1. a multiplexed high gain operational amplifier means having invertingand noninverting inputs and an output and including impedance meanscoupled between said output and said inverting input whereby to add andsubtract signal quantities applied thereto;

2. a plurality of analog signal storage means and a store logic forconnecting the output of said amplifier means to selected ones of saidstorage means;

3. a read logic for connecting selected ones of said analog sensorsignals to said amplifier inputs, said read logic also connectingselected ones of said storage means to said amplifier inputs whereby toprovide selective feedback connections for said amplifier means; and

4. a digital memory means for controlling said read and store logics,said memory including a digital program comprising a plurality ofsequentially read words for determining the computations to be performedon said signals, each word comprising word bits for detennining theoperation of of said read and store logic corresponding to thecomputations to be performed; and

d. means coupled with selected ones of said storage means for supplyingtheanalog signals stored thereon to said servomotor means.

14. A sampled data computer for computing a general plural order filterfunction of an analog information signal comprising:

a. a multiplexed high gain differential amplifier means havingnoninverting and inverting inputs, an output and a feedback impedanceconnected from said output to said inverting input for adding andsubtracting analog signals applied to said inputs;

b. a plurality of analog signal storage devices related in number to theorder of the filter function to be performed, the signal stored on oneof said storage devices constituting the output of said computer;

c. a plurality of charge switches corresponding in number to the numberof said storage means for coupling said amplifier output thereto;

d. a plurality of input switches related in number to the order of thefilter function to be perfonned for coupling signals applied thereto tosaid amplifier inputs and an impedance means associated with each switchfor establishing the gain of the signals applied thereto;

e. means supplying said information signal to a first group of saidinput switches for connecting said information signal to saidnoninverting amplifier input, means supplying the signal stored on saidone storage device to a second group of said input switches forconnecting said stored signal to the inverting amplifier input, andmeans supplying the signals stored in said other signal storage devicesto a third group of said input switches for connecting said other storedsignals to said noninverting amplifier input; and

f. a programmed digital memory means for controlling said input andcharge switches, said memory including a plurality of sequentially readdigital words, each word including a plurality of word bits related innumber to said plurality of switches and determining the state of saidswitches, said word sequence determining the sequential operationsrequired for performing said filter function.

15. A sampled data computer for performing predetermined computations onanalog information signals comprismg:

amplifier means having input means and an output;

said input means being responsive to said analog information signals;

a plurality of analog signal storage means responsive to said amplifieroutput;

a plurality of switch means having conducting and nonconducting statesfor coupling said amplifier output to said signal storage means and forcoupling said storage means back to said amplifier input means forcombining the signals stored therein with said information signals;

digital memory means connected to control said plurality of switch meansin accordance with a predetermined program, said program comprising aplurality of sequential word instructions, each word comprising aplurality of bits corresponding to said plurality of switches forcontrolling the states of said switches, said program determining thecomputation to be performed on said analog information signal; and

an output means coupled with at least one of said signal storage meansand responsive to the resultant signal stored therein.

16. The sampled data computer as set forth in claim 15 wherein saidplurality of switch means comprises:

a plurality of output switch means having conducting and nonconductingstates for selectively coupling said amplifier output to selected onesof said signal storage means; and

combining the signals stored therein with said information signals.

1. A sampled data computer for performing predetermined computation onanalog information signals comprising: a. a high gain differentialamplifier means having noninverting and inverting inputs and an outputand an impedance means coupling said output to said inverting input foradding and subtracting signals applied to said amplifier inputs; b.means supplying analog information signals to at least one of saidamplifier inputs; c. a plurality of analog signal storage meansresponsive to the output of said amplifier; d. a plurality of switchmeans having conducting and nonconducting states for connecting saidamplifier output to said signal storage means and for connecting saidstorage means back to said amplifier inputs for combining the signalsstored therein with said information signals; e. digital memory meansconnected to control said plurality of switch means in accordance with apredetermined program, said program comprising a plurality of sequentialword instructions, each word comprising a plurality of bitscorresponding to said plurality of switches for controlling the statesof said switches, said program determining the computation to beperformed on said analogue information signal; and f. an output meanscoupled with at least one of said signal storage means and responsive tothe resultant signal stored thereon.
 2. The sampled data computer as setforth in claim 1 wherein said analog storage means comprises capacitordevices.
 2. a plurality of analog signal storage means and a store logicfor connecting the output of said amplifier means to selected ones ofsaid storage means;
 3. a read logic for connecting selected ones of saidanalog sensor signals to said amplifier inputs, said read logic alsoconnecting selected ones of said storage means to said amplifier inputswhereby to provide selective feedback connections for sAid amplifiermeans; and
 3. The sampled data computer as set forth in claim 1 whereinsaid switching devices comprise electronic switches of the transistortype.
 4. a digital memory means for controlling said read and storelogics, said memory including a digital program comprising a pluralityof sequentially read words for determining the computations to beperformed on said signals, each word comprising word bits fordetermining the operation of of said read and store logic correspondingto the computations to be performed; and d. means coupled with selectedones of said storage means for supplying the analog signals storedthereon to said servomotor means.
 4. The sampled data computer as setforth in claim 1 for computing the integral of said information signalwherein: a. said information signal is applied to said noninvertinginput of said amplifier; b. said signal storage means comprises at leastfirst and second signal storage devices; c. said plurality of switchescomprises at least first and second switches for selectively connectingsaid amplifier output to said first and second storage devicesrespectively and third and fourth switches for selectively connectingthe signal stored on said first and second storage devices respectivelyback to the noninverting input of said amplifier; d. said digital memorysupplied at least two sequential instruction words repeated over a timeperiod each comprising at least four bits, the first instruction wordbits being such that said first and fourth switches are closed and saidsecond and third switches are open whereby to apply the signal stored onsaid second storage device to said amplifier input and to apply saidamplifier output to said first signal storage device, and the secondinstruction word bits being such that second and third switches areclosed and said first and fourth switches are open whereby to apply thesignal stored on said first storage device to said amplIfier input andto apply said amplifier output to said second signal storage device, andso on; and wherein e. said output means is coupled with said secondsignal storage device.
 5. The sampled data computer as set forth inclaim 4 further including: additional switch means and additionaldigital word and word bits for connecting the output signal stored onsaid second signal storage means to the inverting input of saidamplifier for opposing said information signal whereby to provide a lowpass filtering function of said analog information signal.
 6. Thesampled data computer as set forth in claim 1 for limiting the value ofsaid information signal to any desired value wherein: a. saiddifferential amplifier output to said inverting input coupling meansincludes means for limiting the magnitude of said amplifier output to apredetermined fixed value and limiter switch means having conducting andnonconducting states for rending said limiting means effective andnoneffective; and further including; b. variable impedance meanscoupling said information signal to the noninverting input of saidamplifier and including switch means for determining the impedance tosaid signal whereby to determine the gain thereof; and c. said signalstorage means includes at least first and second storage means; andwherein d. said programmed digital memory includes a first instructionword for controlling said switch means such as to select the gain ofsaid information signal, limit the same to said predetermined value andsupply said limited signal to said first signal storage means, and asecond instruction word for controlling said switch means such as torender said limiting means noneffective, supply said stored signal tosaid variable impedance means whereby to vary the value thereof inaccordance with said reciprocal impedance value, and for storing theresulted signal in said second storage means.
 7. The sampled datalimiter as set forth in claim 6 further including means responsive tosaid information signal and the output of said second signal storagemeans for supplying an output in accordance with the differencetherebetween whereby to provide a deadband function.
 8. The sampled datacomputer as set forth in claim 1 for computing the product of two analoginput signals wherein: a. said means supplying analog informationsignals includes switching means for supplying two information signalsto said noninverting amplifier input and one of said information signalsto said inverting amplifier input; wherein b. said signal storage meansincludes at least four signal storage means; further including c. asquaring circuit including switching means for coupling the output ofone of said storage means to the noninverting input of said amplifier;and further including d. impedance means including switching means forcoupling a predetermined portion of the signals stored on second andthird of said storage means to said noninverting input; and wherein e.said programmed digital memory includes a group of instruction words forcontrolling said switch means such as to store signals proportional tothe squares of the sum and difference of said input signals on saidsecond and third storage means, respectively, and a further instructionword for controlling said switching means such as to supply the signalsstored on said second and third storage means to said impedance meansand the output of said amplifier to the fourth of said storage means,whereby the signal stored thereon is proportioned to the product of saidinput signals.
 9. The sampled data multiplier as set forth in claim 8wherein said group of instruction words comprises a first instructionword for controlling said switching means such as to store on said onestorage means the sum of said input signals, a second instruction wordfor controlling said switching such as to couple the signal stored insaid one storage means to said squaring circuit and to store the Outputof said amplifier on second of said storage means, a third instructionword for controlling said switching means such as to store on said onestorage means the difference of said input signals, and a fourthinstruction word for controlling said switch such as to couple thesignal stored on said one storage means to said squaring circuit and tostore the output of said amplifier on said third storage means.
 10. Asampled data computer system for performing a plurality of computationson a plurality of analog input signals and for supplying analog outputsignals proportional to predetermined functions of said input signals,said system comprising: a. a multiplexed high gain differentialamplifier means having inverting and noninverting inputs and an outputand including a feedback impedance connecting said output to saidinverting input whereby to add and subtract signal quantities appliedthereto; b. a plurality of analog signal storage means; c. a pluralityof output switching devices having conducting and nonconducting statesfor selectively connecting said amplifier output to corresponding onesof said signal storage means depending upon the states thereof wherebyto store said amplifier output in said selected storage means; d. aplurality of input switching devices having conducting and nonconductingstates for selectively connecting a plurality of signals to saidamplifier inputs depending upon the states thereof, said plurality ofsignals including said analog input signals and selected ones of thesignals stored on said storage means; e. a programmed digital memorymeans for determining the functions to be performed on said inputsignals, said digital memory providing sequentially read words, eachword comprising a plurality of bits corresponding to said plurality ofswitch devices, whereby to control the sequence and order respectivelyof switch states required for performing said functions; and f. meanscoupled with selected ones of said signal storage means for supplyinganalog output signals corresponding to the resultant signals storedthereon.
 11. The sampled data computer as set forth in claim 10 furtherincluding a plurality of impedances coupled between said input switchesand said amplifier inputs for determining the gains of said selectedsignals.
 12. The sampled data computer as set forth in claim 11 whereinat least one of said impedances comprises a resistance ladder networkand a plurality of switches for selecting the resultant impedancethereof, and wherein said digital program memory includes word bits forcontrolling said ladder switches whereby to program the gains of saidselected input signals in accordance with the function to be performed.13. A digitally controlled, analog servomechanism comprising: a. aplurality of sensors for producing a plurality of analog signals eachproportional to one of a plurality of conditions to be controlled; b.servomotor means for controlling said conditions; c. sampled datacomputer means responsive to said sensor signals for performing aplurality of predetermined computations thereon and for supplyingresultant output signals to said servomotor means whereby to controlsaid conditions in accordance with said predetermined computations, saidcomputer means comprising:
 14. A sampled data computer for computing ageneral plural order filter function of an analog information signalcomprising: a. a multiplexed high gain differential amplifier meanshaving noninverting and inverting inputs, an output and a feedbackimpedance connected from said output to said inverting input for addingand subtracting analog signals applied to said inputs; b. a plurality ofanalog signal storage devices related in number to the order of thefilter function to be performed, the signal stored on one of saidstorage devices constituting the output of said computer; c. a pluralityof charge switches corresponding in number to the number of said storagemeans for coupling said amplifier output thereto; d. a plurality ofinput switches related in number to the order of the filter function tobe performed for coupling signals applied thereto to said amplifierinputs and an impedance means associated with each switch forestablishing the gain of the signals applied thereto; e. means supplyingsaid information signal to a first group of said input switches forconnecting said information signal to said noninverting amplifier input,means supplying the signal stored on said one storage device to a secondgroup of said input switches for connecting said stored signal to theinverting amplifier input, and means supplying the signals stored insaid other signal storage devices to a third group of said inputswitches for connecting said other stored signals to said noninvertingamplifier input; and f. a programmed digital memory means forcontrolling said input and charge switches, said memory including aplurality of sequentially read digital words, each word including aplurality of word bits related in number to said plurality of switchesand determining the state of said switches, said word sequencedetermining the sequential operations required for performing saidfilter function.
 15. A sampled data computer for performingpredetermined computations on analog information signals comprising:amplifier means having input means and an output; said input means beingresponsive to said analog information signals; a plurality of analogsignal storage means responsive to said amplifier output; a plurality ofswitch means having conducting and nonconducting states for couplingsaid amplifier output to said signal storage means and for coupling saidstorage means back to said amplifier input means for combining thesignals stored therein with said information signals; digital memorymeans connected to control said plurality of switch means in accordancewith a predetermined program, said program comprising a plurality ofsequential word instructions, each word comprising a plurality of bitscorresponding to said plurality of switches for controlling the statesof said switches, said program determining the computation to beperformed on said analog information signal; and an output means coupledwith at least one of said signal storage means and responsive to theresultant signal stored therein.
 16. The sampled data computer as setforth in claim 15 wherein said plurality of switch means comprises: aplurality of output switch means having conducting and nonconductingstates for selectively coupling said amplifier output to selected onesof said signal storage means; and a plurality of feedback switch meanshaving conducting and nonconducting states for seLectively coupling saidsignal storage means back to said amplifier input means for combiningthe signals stored therein with said information signals.